Monitors and utilizes computers and test equipment for more than 6 hours a day.Performs required tasks at various heights (e.g., standing or sitting).Frequently transports and installs equipment up to 5 lbs.Frequently transports between offices, buildings, and campuses up to ½ mile.Master's or PhD degree in Science, Engineering, or related field. Good English oral and written communications skills.Good knowledge of device level electrical measurement.Experience in mixed-signal integrated circuits design is plus.Good knowledge of Mentor Calibre nmDRC, nmLVS, and PEX.Familiar with Cadence Skill, parameterized cells (Pcell), CDF, and callbacks.Familiar with of Cadence Virtuoso layout editor and ADE.Hands on experience in mask layout or PDK development.Master's or PhD degree in Electrical Engineering or similarly relevant subject.He/she will support mask layout and/or PDK development to create device level layout/pcells, debug DRC/LVS errors, evaluate PDKs, maintain layout database, and support electrical measurement. The candidate will apply mask layout and verification expertise to the development of the next generation fingerprint sensors based on LTPS process technology. Qualcomm is looking for a motivated candidate with experience in mixed-signal circuits layout, verification, and PDK development.
Job Area:Engineering Group, Engineering Group > Hardware Engineeringīe a part of a dynamic and innovative team to define the next generation of innovative fingerprint sensor solutions for portable mobile devices.